
all: compile run
	echo "make all"

build: compile
	xvlog --sv axil_interface.sv
	xvlog --sv axil_ram.v 
	xvlog --sv dpi_interface.sv
	xvlog --sv axil_dpi_top_module.sv
	xelab -debug all --snapshot sp1 axil_dpi_top_module
	xsim sp1


compile:
	xsc --gcc_compile_options -I../switchboard/cpp axil_dpi_bridge.cc

clean:
	rm -rf .Xil xsim.dir
	rm -f dump.vcd sp1.wdb webtalk* xelab* xsim* xvlog*
	rm -f *.so xsc.log xsc.pb

	rm -f *.q *.wcfg
	rm -f *.vcd
	rm -rf obj_dir build

run:
	python3 run_all.py --tool verilator

test_axi:
	xvlog --sv axil_interface.sv
	xvlog --sv axil_ram.v 
	xvlog --sv axil_interface_test.sv 
	xelab -debug all --snapshot sp1 axil_interface_test
	xsim sp1
# open_vcd
# log_vcd *
# add_wave *
# run 20ns
# save_wave_config all_signals.wcfg
# close_vcd
# quit

test_dpi: compile run_dpi
	echo "make test_dpi"

run_dpi:
	python3 dpi_interface_test.py --tool verilator
# xvlog --sv dpi_interface.sv
# xvlog --sv dpi_interface_test.sv
# xelab -debug all --snapshot sp1 dpi_interface_test
# xsim sp1
